may 2012 FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMC8327L rev.c1 1234 5 dddd g s s s bottom top mlp 3.3x3.3 6 7 8 s s s g d d d d FDMC8327L n-channel powertrench ? mosfet 40 v, 14 a, 9.7 m features ? max r ds(on) = 9.7 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 12.5 m at v gs = 4.5 v, i d = 10 a ? low profile - 0.8mm max in power 33 ? 100% uil test ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced power trench ? process that has been especially tailored to minimi ze the on-state resistance and yet maintain superior switching performance. application ? dc-dc conversion mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 40 v v gs gate to source voltage 20 v i d drain current - continuous (package limited) t c = 25 c 14 a - continuous (silicon limited) t c = 25 c 43 - continuous t a = 25 c (note 1a) 12 - pulsed 60 e as single pulse avalanche energy (note 3) 25 mj p d power dissipation t c = 25 c 30 w power dissipation t a = 25 c (note 1a) 2.3 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case (note 1) 4.2 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity FDMC8327L FDMC8327L power 33 13 ? 12 mm 3000 units
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMC8327L rev.c1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 40 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 22 mv/c i dss zero gate voltage drain current v ds = 32 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.0 1.7 3.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 12 a 7.4 9.7 m v gs = 4.5 v, i d = 10 a 9.4 12.5 v gs = 10 v, i d = 12 a, t j = 125 c 11 14.5 g fs forward transconductance v dd = 5 v, i d = 12 a 52 s c iss input capacitance v ds = 20 v, v gs = 0 v, f = 1 mhz 1235 1850 pf c oss output capacitance 347 520 pf c rss reverse transfer capacitance 21 35 pf r g gate resistance 0.1 0.6 1.3 t d(on) turn-on delay time v dd = 20 v, i d = 12 a, v gs = 10 v, r gen = 6 8.4 17 ns t r rise time 2.2 10 ns t d(off) turn-off delay time 20 32 ns t f fall time 2.2 10 ns q g(tot) total gate charge v gs = 0v to 10 v v dd = 20 v, i d = 12 a 18.5 26 nc q g(tot) total gate charge v gs = 0v to 5 v 9.7 14 nc q gs gate to source charge 3.3 nc q gd gate to drain ?miller? charge 2.6 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 1.8 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 12 a (note 2) 0.8 1.3 t rr reverse recovery time i f = 12 a, di/dt = 100 a/s 32 51 ns q rr reverse recovery charge 10 20 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25 c; n-ch: l = 0.3 mh, i as = 13 a, v dd = 36 v, v gs = 10 v. g df ds sf ss g df ds sf ss 53 c/w when mounted on a 1 in 2 pad of 2 oz copper a. 125 c/w when mounted on a minimum pad of 2 oz copper b.
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMC8327L rev.c1 typical characteristics t j = 25 c unless otherwise noted figure 1. 0.0 0.3 0.6 0.9 1.2 1.5 0 10 20 30 40 50 60 v gs = 6 v v gs = 3 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 4.5 v v gs = 4 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 102030405060 0 1 2 3 4 v gs = 6 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4 v v gs = 4.5 v v gs = 3 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 5 10 15 20 25 30 t j = 125 o c i d = 12 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 50 60 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.00.20.40.60.81.01.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMC8327L rev.c1 figure 7. 0 4 8 121620 0 2 4 6 8 10 i d = 12 a v dd = 24 v v dd = 16 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v gate charge characteristics figure 8. 0.1 1 10 40 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 30 1 10 20 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 limited by package v gs = 4.5 v r t jc = 4.2 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 10 s 1 s dc 100 ms 10 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c figure 12. 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 300 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMC8327L rev.c1 figure 13. junction-to-ambient transient thermal response curve 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMC8327L rev.c1 dimensional outline and pad layout
FDMC8327L n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMC8327L rev.c1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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